1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC), and more particularly, to apparatus and methods for generating a write control signal in a semiconductor IC.
2. Related Art
Conventional Dynamic Random Access Memory (DRAM) devices operate at high frequencies. In order to test such devices, the test equipment used must employ a high-frequency clock. However, since the high-frequency clock used for current test equipment limits the number of usable test channels, the number of parameters or products that can be tested simultaneously is limited. For this reason, the test time and cost may increase.
FIG. 1 is an operational timing view for a semiconductor IC operated by receiving a write control signal (Int.write). The clock signal (CLK) and reference clock signal (DQS) shown in FIG. 1 are high frequency signals. In the timing view shown in FIG. 1, a write latency WL is equal to 2, and a burst length BL is equal to 4. Four external data bits D0, D1, D2 and D3 are input into the DRAM. Each of the external data bits D0, D1, D2 and D3 can be input into a DRAM core while being synchronized with a rising edge and falling edge of the reference clock signal (DQS). The write control signal (Int.write) is generated after the write latency WL period and half the burst length BL/2. The four external data bits D0, D1, D2 and D3 are serially input into the DRAM, but as the write control signal (Int.write) is enabled, the four external data bits D0, D1, D2 and D3 are transmitted to the DRAM core region in parallel using the high-speed clock signal (CLK). This is represented in the figure as internal data bits Di0, Di1, Di2, and Di3.
As mentioned above, in order to test the DRAM operation, the test equipment must employ high-frequency clock channels to test the high-frequency DRAM. However, as described above, the number of usable channels for high-frequency clock operation is limited in conventional test equipment. To solve this problem, there has been suggested a scheme, in which the high-frequency clock is used for the clock signal (CLK) and the reference clock signal (DQS), and a lower frequency clock signal, e.g., with a period at least twice that of the high frequency clock signal (CLK) is used for remaining data test pins of the test equipment.
FIG. 2 is a diagram illustrating the operational timing of such a scheme. As can be seen, the transmission speed of the external data does not correspond to the clock speed, so only two of four data are transmitted when the write control signal (Int.write) is enabled, i.e., only two data bits are transmitted to the DRAM core region in parallel after the write control signal (Int.write) is enabled
In addition, as shown in FIG. 3, there has been suggested a scheme in which the lower frequency clock is used for the reference clock signal (DQS) and a high-frequency clock is used for the data signals. However, in this case, the external data bits D0, D1, D2 and D3 are input into the DRAM in synchronization with the rising edge and falling edge of the reference clock signal (DQS). Accordingly, only two of four data bits are transmitted when the write control signal (Int.write) is enabled, so the desired test result cannot be obtained.
Therefore, conventional test equipment is inefficient to test various parameters of high-frequency memory apparatus, such as high frequency DRAMs. Additionally, exchanging current test equipment can result in significant cost.